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Design Verification Engineer Interview Experience - Bengaluru, Karnataka

August 1, 2024
Positive ExperienceNo Offer

Process

They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow.

Then questions were on the digital domain.

Questions on Verilog and C/C++:

  • STA
  • Verilog project

Questions

What did you understand about this role?

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Interview Statistics

The following metrics were computed from 4 interview experiences for the Intel Design Verification Engineer role in Bengaluru, Karnataka.

Success Rate

25%
Pass Rate

Intel's interview process for their Design Verification Engineer roles in Bengaluru, Karnataka is very selective, failing most engineers who go through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Design Verification Engineer interview process in Bengaluru, Karnataka.

Intel Work Experiences