They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow.
Then questions were on the digital domain.
Questions on Verilog and C/C++:
What did you understand about this role?
The following metrics were computed from 4 interview experiences for the Intel Design Verification Engineer role in Bengaluru, Karnataka.
Intel's interview process for their Design Verification Engineer roles in Bengaluru, Karnataka is very selective, failing most engineers who go through it.
Candidates reported having very good feelings for Intel's Design Verification Engineer interview process in Bengaluru, Karnataka.