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Design Verification Engineer Interview Experience - India

October 1, 2021
Negative ExperienceNo Offer

Process

The interview was average. It covered basic electronic questions, including Verilog, SystemVerilog (SV), and UVM basics.

The HR round was disappointing. There was no clear communication from the company regarding the next steps in the process. They repeatedly delayed the process without any updates.

Questions

Questions on:

  • Interface
  • Clocking blocks
  • Assertions
  • UVM
  • X propagation

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Interview Statistics

The following metrics were computed from 7 interview experiences for the Intel Design Verification Engineer role in India.

Success Rate

29%
Pass Rate

Intel's interview process for their Design Verification Engineer roles in India is very selective, failing most engineers who go through it.

Experience Rating

Positive86%
Neutral0%
Negative14%

Candidates reported having very good feelings for Intel's Design Verification Engineer interview process in India.

Intel Work Experiences