You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog.
Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a positive attitude.
What I know about Verilog
The following metrics were computed from 1 interview experience for the Intel Design Verification Engineer role in Malaysia.
Intel's interview process for their Design Verification Engineer roles in Malaysia is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Intel's Design Verification Engineer interview process in Malaysia.