Design Verification Engineer Interview Experience - San Jose, California
Process
It was technical and behavioral. I was asked questions about my resume and all previous experience, as well as technical details of the verification components I used in those projects and other related work.
I would rate them as moderate in complexity.
Questions
UVM, SystemVerilog, and scoreboard-related questions.
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Interview Statistics
The following metrics were computed from 1 interview experience for the Intel Design Verification Engineer role in San Jose, California.
Success Rate
Intel's interview process for their Design Verification Engineer roles in San Jose, California is incredibly easy as the vast majority of engineers get an offer after going through it.
Experience Rating
Candidates reported having very good feelings for Intel's Design Verification Engineer interview process in San Jose, California.
Intel Work Experiences
- 5.0Great teamworkDesign Verification Engineer • Current EmployeeSan Jose, California, United StatesOctober 9, 2024Pros: Good communication and teamwork.Cons: Bad management which led to its downfall.
- 4.0Great company to work atDesign Verification Engineer • Current EmployeeSan Jose, California, United StatesApril 12, 2023Pros: Flexible schedule when working from home.Cons: Sometimes a job can be very stressful.
- 5.0Great Insurance, Needs More TimeDesign Verification Engineer • Current EmployeeSan Jose, California, United StatesOctober 13, 2022Pros: Everything, basically. We have good medical insurance.Cons: Nothing until now. I need more time.
Intel Interview Questions
