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Design Verification Engineer Interview Experience - Santa Clara, California

April 4, 2024
Negative ExperienceNo Offer

Process

There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.

Questions

They asked about my UVM design verification project.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Design Verification Engineer role in Santa Clara, California.

Success Rate

0%
Pass Rate

Intel's interview process for their Design Verification Engineer roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral0%
Negative100%

Candidates reported having very negative feelings for Intel's Design Verification Engineer interview process in Santa Clara, California.

Intel Work Experiences