There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
They asked about my UVM design verification project.
The following metrics were computed from 1 interview experience for the Intel Design Verification Engineer role in Santa Clara, California.
Intel's interview process for their Design Verification Engineer roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Intel's Design Verification Engineer interview process in Santa Clara, California.