I received an email to schedule a 30-45 minute technical phone interview. They clearly mentioned technical questions would cover RTL design/Verilog/SystemVerilog, digital design, validation, synthesis steps, and basic analog questions.

I had not taken any courses on Verilog or SystemVerilog and had no experience with them. The only topics I was familiar with were digital design and VHDL programming. Consequently, I did not perform well in the interview.

They asked many SystemVerilog and analog questions. The interviewer was unwilling to repeat questions when I asked for clarification. Based on my first answer, she decided not to move forward with me.

1. Assertion in SystemVerilog

2. Differences between tasks and functions in SystemVerilog

3. CMOS problems

4. Capacitors connected in series and parallel problems: Find total capacitance, charge, and voltage across the capacitors.

5. What are generator clocks?

6. Difference between reg, wire, and logic

7. Details on blocking and non-blocking assignments

8. Inheritance concept in SystemVerilog and how to implement it

9. Explain the full adder truth table. Please explain in words. I made a great mess by explaining line by line with numbers.

10. Virtual interfaces

11. How to implement synchronous reset and asynchronous reset