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Logic Verification Engineer (RCG) Interview Experience - Santa Clara, California

February 1, 2011
Neutral ExperienceNo Offer

Process

Interviewed over the phone for a position with Intel, Santa Clara.

Most phone screens are asked from a set list, available by a simple Google search for "Intel Interview Questions". The on-site interview consists of 5 interviews: 4 technical and 1 with the group manager. The technical questions were more difficult than those asked during the phone interview.

Schedule

  • 10:00 AM to 11:00 AM – Circuit Fundamentals (logic design, speed considerations based on physical layout)
  • 11:00 AM to Noon – Logic/Validation (*Strayed from topics during this interview, interviewer seemed preoccupied)

Lunch

  • 1:00 PM to 2:00 PM – Computer Architecture & Logic Verification (Logic testing, cache layout/controllers)
  • 2:00 PM to 3:00 PM – Basic Unix commands, tools, scripts, etc. (Whiteboard "Can you show me **** in VHDL/C/Unix?")
  • 3:00 PM to 4:00 PM – Wrap-up (Strengths/weaknesses, interests, how would you handle A/B/C?)

Technical interviews are not difficult; most ECE or CS students will get through alright.

Aside from interviews, I found the on-site useful as I saw where and with whom I would be working. Generally dark, gray/white/blue color scheme, cubicles. Also, there is an "Intel employee type." Good place for processor design careers.

Questions

Discuss addressing schemes.

Draw a distributed memory system layout.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Logic Verification Engineer (RCG) role in Santa Clara, California.

Success Rate

0%
Pass Rate

Intel's interview process for their Logic Verification Engineer (RCG) roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Intel's Logic Verification Engineer (RCG) interview process in Santa Clara, California.

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