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Pre Silicon Validation Engineer Interview Experience

August 28, 2020
Neutral ExperienceNo Offer

Process

Phone Interview.

I had applied through the company website. It's an SoC team based in Hudson, MA.

Try to analyze your resume from the POV of a Verification/Validation engineer. That's the answer.

I was told that the intern interview would be basic.

Questions

Intel, MA

This document outlines an interview experience, covering the following key areas:

  1. Introduction to the project and current activities.
  2. Overview of my education and professional skills.
  3. The interviewer, a verification engineer, identified bugs in my resume before discussing the project.
  4. Moving on, the interviewer asked detailed questions about my projects, including design specifications, test plans, and architecture integration.
  5. I discussed an RTL project and was asked to verify it.
  6. Questions covered testbench setup and verification methodologies.
  7. UVM testbench setup was specifically addressed.
  8. The concept of a reference model and its application was explored.
  9. Rule-based verification, a technique used at Intel that I was unfamiliar with, was explained.
  10. At this point, I felt exhausted. The interviewer then shifted to Python to assess my coding abilities.
  11. After discussing my Python work experience, the interviewer stated I was not proficient in Python.
  12. The interview continued with Computer Architecture topics, including stages of a pipeline.
  13. I was asked about stall situations in a pipeline.
  14. The necessity of branch predictors was discussed.
  15. Various types of hazards were covered.
  16. The reason for coherency requirements was questioned.
  17. The definition of a bus was asked.
  18. The exclusive state was discussed.
  19. The transition from the E to M state was explored.
  20. I was asked about the scenario where two processors attempt to write to the same cache location.
  21. A specific scenario involving four processors and four caches was presented, asking what would happen if P0 and P1 had a shared value at a location, and P4 attempted to write to it.

The time concluded with the interviewer asking if I had any questions for them.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Pre Silicon Validation Engineer role in United States.

Success Rate

0%
Pass Rate

Intel's interview process for their Pre Silicon Validation Engineer roles in the United States is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Intel's Pre Silicon Validation Engineer interview process in United States.

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