There were two rounds, one in each week.
In the first round, I was asked about projects and questions on related topics like UVM, SystemVerilog, and coverage. Other questions were on logic design, C++, Verilog, and computer architecture, such as virtual memory.
In the second round, the interview was conducted by the team lead. Questions focused on projects (in detail), a puzzle question, and a design question on a priority encoder.
Design a 16-to-4 priority encoder using a 4-to-2 priority encoder.
The following metrics were computed from 1 interview experience for the Intel Pre-Silicon Verification role in United States.
Intel's interview process for their Pre-Silicon Verification roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's Pre-Silicon Verification interview process in United States.