Applied online in January 2018 and had a 38-minute phone interview in April. They asked basic questions regarding memory storage cell structures, MOSFET and BJT comparison, some basic statistics questions, and questions regarding the resume.
Then, I received a call the next day to set up an onsite interview at Intel's Folsom office for 3 hours with 4 interviewers.
First round: Behavioral, with some questions regarding the resume. Second round: Computer architecture, with some data structures questions on the side. Third round: Why Intel, waveform debugging, and statistical analysis using root cause analysis. Fourth round: Analog and setup and hold time analysis.
Still waiting on the result.
How to debug setup and hold time on silicon?
The following metrics were computed from 8 interview experiences for the Intel Product Development Engineer role in Folsom, California.
Intel's interview process for their Product Development Engineer roles in Folsom, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Intel's Product Development Engineer interview process in Folsom, California.