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Product Development Engineer Interview Experience - Folsom, California

June 1, 2011
Positive ExperienceGot Offer

Process

The interview process started with a phone interview in late April.

The interviewer asked a series of questions on:

  • DFT Techniques
  • PERL/TK
  • PCI Express

I was able to answer all questions satisfactorily.

I was shortlisted for FM Rush Interviews in early June.

The interview consisted of three rounds of technical and behavioral questions from senior technical staff.

The first round focused on DFT basics and how I could perform SCAN techniques on different chips, along with some behavioral questions.

The second round consisted of technical questions related to various lab bench testing devices such as oscilloscopes, logic analyzers, and functional waveform generators. The interviewer also asked questions about various projects I had completed during my Master's that involved the use of lab equipment, and a few questions regarding jitter and eye patterns were asked.

The third round concerned device physics, basic circuit design questions, and an in-depth analysis of some of my projects.

Questions

What are SCAN and JTAG techniques?

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Interview Statistics

The following metrics were computed from 8 interview experiences for the Intel Product Development Engineer role in Folsom, California.

Success Rate

50%
Pass Rate

Intel's interview process for their Product Development Engineer roles in Folsom, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive50%
Neutral25%
Negative25%

Candidates reported having very good feelings for Intel's Product Development Engineer interview process in Folsom, California.

Intel Work Experiences