The interview process started with a phone interview in late April.
The interviewer asked a series of questions on:
I was able to answer all questions satisfactorily.
I was shortlisted for FM Rush Interviews in early June.
The interview consisted of three rounds of technical and behavioral questions from senior technical staff.
The first round focused on DFT basics and how I could perform SCAN techniques on different chips, along with some behavioral questions.
The second round consisted of technical questions related to various lab bench testing devices such as oscilloscopes, logic analyzers, and functional waveform generators. The interviewer also asked questions about various projects I had completed during my Master's that involved the use of lab equipment, and a few questions regarding jitter and eye patterns were asked.
The third round concerned device physics, basic circuit design questions, and an in-depth analysis of some of my projects.
What are SCAN and JTAG techniques?
The following metrics were computed from 8 interview experiences for the Intel Product Development Engineer role in Folsom, California.
Intel's interview process for their Product Development Engineer roles in Folsom, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Intel's Product Development Engineer interview process in Folsom, California.