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Reliability Engineer Interview Experience - Santa Clarita, California

January 1, 2012
Positive ExperienceGot Offer

Process

First, a phone interview was conducted, with many technical questions about basic semiconductor device physics.

Then, an on-site interview invitation was received.

The interview process included:

  • A 45-minute presentation.
  • Meeting six engineers consecutively, one hour per person.

Half of the questions were behavioral, and half were technical, with a primary focus on PhD research.

A call was received the next day offering the position.

Questions

What is the physical meaning of the threshold voltage of a transistor?

How do you define it?

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Reliability Engineer role in Santa Clarita, California.

Success Rate

100%
Pass Rate

Intel's interview process for their Reliability Engineer roles in Santa Clarita, California is incredibly easy as the vast majority of engineers get an offer after going through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Reliability Engineer interview process in Santa Clarita, California.

Intel Work Experiences