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Soc Design Verification Engineer Interview Experience - Fort Collins, Colorado

March 1, 2016
Positive ExperienceNo Offer

Process

The entire interview experience was very good.

Had a brief phone round where I was asked questions on computer architecture fundamentals like cache and pipelining.

Then onsite, I had 5 rounds: 4 technical and 1 behavioral.

  1. The first round was on computer architecture and problem-solving, where I was asked questions on cache coherency and one design problem for a 4-way set associative cache.
  2. The second round was on logic design, where I had to design an FSM for a vending machine and answer a few other timing and K-map simplification questions.
  3. The third round was on validation, which was more of a discussion covering many verification concepts, starting from assertions, coverage, and golden test vectors.

Then, after lunch, I had the behavioral round where the manager mostly went into the details of my resume.

My fifth round was on software, which had a lot of pseudocodes. I had to correct them, make some changes, and also answer many one-line questions covering all OOP concepts, data structures, etc.

Overall, my interview experience was excellent, and I was expecting an offer but don't know why they rejected me.

Questions

Computer Architecture, Logic Design, Validation, Software, Behavioral.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Soc Design Verification Engineer role in Fort Collins, Colorado.

Success Rate

0%
Pass Rate

Intel's interview process for their Soc Design Verification Engineer roles in Fort Collins, Colorado is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Soc Design Verification Engineer interview process in Fort Collins, Colorado.

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