I was interviewed for a co-op position, for which I applied a long time ago. This position is 6-9 months in duration.
The interview was mostly based on my resume, with follow-up questions on how to verify my RTL design if I hadn't written the RTL code and was assuming it as a black box. The interviewer mostly concentrated on cases I would consider for verification.
SystemVerilog Basics. Didn't touch upon UVM. OOPS concepts, virtual keyword, etc.
Given an Adder, what test cases would you consider for verification?
The following metrics were computed from 1 interview experience for the Intel SoC Verification Engineer role in San Jose, California.
Intel's interview process for their SoC Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's SoC Verification Engineer interview process in San Jose, California.