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Validation Engineer Interview Experience - Austin, Texas

September 1, 2008
Positive ExperienceGot Offer

Process

I was interviewed by over half a dozen people over the course of a day. Almost all questions were technical and delivered by senior technical staff.

For example, I was asked to:

  • Draw a system diagram (HW & SW stacks).
  • Label the components (CPU, southbridge, IRP, IRQL, DPC).
  • Answer questions regarding their function (MMIO, paging, interrupt handling, DMA, cache coherency, snooping, IRP & IRQL handling), starting general and progressing as deep as I was able.

Some interviewers were fishing, looking for specific answers to specific questions, rather than asking open-ended questions that might allow me to open up and shine.

Hints of behavioral questions were mixed into one or two casual questions, but none of the point-blank "tell me about a time" questions were asked.

Two interviews were conducted by managers.

One was the reporting manager, who asked what I was good at, what I liked to do, and where I saw myself going. They were very open and understanding towards growth and change, suggesting that I could use the position as an opportunity to springboard into other positions when things got stale.

The other manager was a director who got straight to the point: compensation, availability, and response turnaround time.

Impressions: It seemed that people were wound tightly and schedules were very aggressive. The environment was business-like and to the point; only type-A personalities need apply.

Questions

What are the APICs, where are they, and how do they function?

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Interview Statistics

The following metrics were computed from 3 interview experiences for the Intel Validation Engineer role in Austin, Texas.

Success Rate

0%
Pass Rate

Intel's interview process for their Validation Engineer roles in Austin, Texas is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Validation Engineer interview process in Austin, Texas.

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