I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider.
When it came to UVM, I was asked for the difference between a sequence and a sequencer.
UVM Phase
Mailbox in SV
The following metrics were computed from 3 interview experiences for the Intel Verification Engineer role in Bengaluru, Karnataka.
Intel's interview process for their Verification Engineer roles in Bengaluru, Karnataka is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Intel's Verification Engineer interview process in Bengaluru, Karnataka.