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Verification Engineer Interview Experience - Bengaluru, India

February 1, 2020
Positive ExperienceGot Offer

Process

I was interviewed and demonstrated depth of knowledge in UVM, SV, basic design concepts for FIFOs, and Verilog code for a clock divider.

When it came to UVM, I was asked for the difference between a sequence and a sequencer.

Questions

UVM Phase

Mailbox in SV

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Interview Statistics

The following metrics were computed from 3 interview experiences for the Intel Verification Engineer role in Bengaluru, Karnataka.

Success Rate

33%
Pass Rate

Intel's interview process for their Verification Engineer roles in Bengaluru, Karnataka is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Verification Engineer interview process in Bengaluru, Karnataka.

Intel Work Experiences