Great Learning, Slow Growth
Great Learning, Slow Growth
- Flexible working hours
- Exposure to a vast amount of resources for self-learning
- Poor strategy execution
- Less room for promotion due to budget cut
Try to retain the talents instead of hiring fresh graduates with higher market salaries.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
First, there were some technical questions, and two technical leaders came to the interview. The questions were not very hard, including some basic ones. The technical leaders paid more attention to the value the interviewee could supply to the compa
Design Verification Engineer
You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
Design Verification Engineer
Xi'an, Shaanxi, ChinaOctober 1, 2010First, there were some technical questions, and two technical leaders came to the interview. The questions were not very hard, including some basic ones. The technical leaders paid more attention to the value the interviewee could supply to the compa
Design Verification Engineer
MalaysiaDecember 30, 2024You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit
Design Verification Engineer
Santa Clara, California, United StatesApril 4, 2024There was an initial 30-minute call with the director, and then I was scheduled for a 1-hour call with the manager. The manager was in no mood to take the interview. Terrible experience.
