Great Learning, Busy Colleagues
Great Learning, Busy Colleagues
The learning curve will always be upwards.
Colleagues are too busy to get help.
Additional Ratings
Was this helpful?
Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
It was technical and behavioral. I was asked questions about my resume and all previous experience, as well as technical details of the verification components I used in those projects and other related work. I would rate them as moderate in complex
Design Verification Engineer
First round with the hiring manager. Five rounds of technical interviews, each lasting one hour. The last round was extended to two hours with significant grilling. Panelists included individuals with extensive experience, up to the Principal Engin
Design Verification Engineer
Bengaluru, Karnataka, IndiaAugust 1, 2024They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
San Jose, California, United StatesMay 1, 2021It was technical and behavioral. I was asked questions about my resume and all previous experience, as well as technical details of the verification components I used in those projects and other related work. I would rate them as moderate in complex
Design Verification Engineer
IndiaSeptember 13, 2021First round with the hiring manager. Five rounds of technical interviews, each lasting one hour. The last round was extended to two hours with significant grilling. Panelists included individuals with extensive experience, up to the Principal Engin
