Great Place, Sometimes Low Raises
Great Place, Sometimes Low Raises
Great environment. Good benefits. Good infrastructure.
Annual increases are sometimes not good.
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Intel Interview Questions
Intel Interview Experiences
SoC Verification Engineer
There were seven rounds of technical interviews. Each took place one-on-one with all team members. After the first and second rounds, there were four more rounds and one final round. Questions on SV, UVM, assertions, functional, and code coverage we
SoC Verification Engineer
The interview will be based on course projects, basics of digital electronics, Digital VLSI design, CAD for IC design, VLSI design flow steps, etc., and basics of MOSFET devices. There was no written test.
SoC Verification Engineer
I was interviewed for a co-op position, for which I applied a long time ago. This position is 6-9 months in duration. The interview was mostly based on my resume, with follow-up questions on how to verify my RTL design if I hadn't written the RTL co
SoC Verification Engineer
Bengaluru, Karnataka, IndiaOctober 1, 2024There were seven rounds of technical interviews. Each took place one-on-one with all team members. After the first and second rounds, there were four more rounds and one final round. Questions on SV, UVM, assertions, functional, and code coverage we
SoC Verification Engineer
IndiaAugust 30, 2019The interview will be based on course projects, basics of digital electronics, Digital VLSI design, CAD for IC design, VLSI design flow steps, etc., and basics of MOSFET devices. There was no written test.
SoC Verification Engineer
San Jose, California, United StatesJune 1, 2023I was interviewed for a co-op position, for which I applied a long time ago. This position is 6-9 months in duration. The interview was mostly based on my resume, with follow-up questions on how to verify my RTL design if I hadn't written the RTL co
