High potential and highly recommended
High potential and highly recommended
No micro-management, supports employee growth
Life balance has lots to do.
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Marvell Technology Interview Experiences
ASIC Design Engineer
I have applied this position on line last year. I have received a phone interview last week and there will be a phone interview this week. Asked the basic questions about the ASIC design and questions about the resume. Clock skew and jitter. Blocking
Hardware Engineer
Referred by a friend to her manager get an video conference(on-site) directly within 3 to 4 weeks. 1 month after the interview I sent a follow-up email to check the hiring status, the manager told me that the hiring was frozen just after my interview
Design Verification Engineer
There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
ASIC Design Engineer
Santa Clarita, CaliforniaJanuary 1, 2016I have applied this position on line last year. I have received a phone interview last week and there will be a phone interview this week. Asked the basic questions about the ASIC design and questions about the resume. Clock skew and jitter. Blocking
Hardware Engineer
Aliso Viejo, CaliforniaMarch 1, 2015Referred by a friend to her manager get an video conference(on-site) directly within 3 to 4 weeks. 1 month after the interview I sent a follow-up email to check the hiring status, the manager told me that the hiring was frozen just after my interview
Design Verification Engineer
California City, CaliforniaNovember 1, 2023There were two technical rounds I attended. Both are on SystemVerilog, digital, and UVM. I suggest brush your digital concepts well. Make sure you work on System Verilog constraint thoroughly.
