I had a tough interview, mainly focused on standard SystemVerilog/ Verilog questions along with some programming questions in designing. Some detailed question of explaining on static timing analysis and clock domain crossing.
Setup time and hold time calculations of a design? Optimization of FPGA design in terms of power, timing while making frequency efficient.
The following metrics were computed from 1 interview experience for the Microchip Technology FPGA/Emulation Engineer role in New York, New York.
Microchip Technology's interview process for their FPGA/Emulation Engineer roles in New York, New York is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Microchip Technology's FPGA/Emulation Engineer interview process in New York, New York.