The process included an initial recruiter screening followed by a longer virtual technical interview with the hiring team.

The interview covered my background, project experience, C++/algorithms/data structures, scripting experience, and some FPGA/EDA-related concepts such as timing analysis and debugging.

Overall, the process was professional and focused on both software fundamentals and domain knowledge.

One question they asked was how I would approach parsing a large Verilog netlist and identifying module instantiations efficiently.