It's like an exam. I received the interview at a college career fair. The test is for a group; many students take it at the same time. There are 6 questions.
Will the CMOS NAND gate speed up by increasing VDD?
Use a min 2-input NAND to build a 3-input NAND.
The following metrics were computed from 1 interview experience for the Micron Technology ASIC Design Engineer role in UCLA, California.
Micron Technology's interview process for their ASIC Design Engineer roles in UCLA, California is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Micron Technology's ASIC Design Engineer interview process in UCLA, California.