It's a SHAM!
I was contacted by an underpaid, rude, no-degree HR for a design verification position.
Since it is shelter in place, all interviews were conducted online.
First round was with one of the team members, which was technical in nature. He asked me about my projects and past experience. Technical questions included constrain random, assertions, and UVM environment.
Next series of online interviews were with people from different groups. Questions varied from OOPS concepts, SystemVerilog, UVM, coverage, Verilog, and digital logic basics. I think I did well with most of them, except for Verilog and digital logic basics. Questions were from school, which I struggled to answer.
Last interview was with the Director/VP. He was very polite and knowledgeable. In fact, all the interviewers were nice, except for the old Indian lady (she should retire).
I got a message from HR the next day that they were interested in moving ahead with me and asked for my base pay expectations. I was hesitant giving a number, but since he was so adamant about a number, I thought of giving a range.
And BOOM! He disappeared. After following up several times and getting vague answers like, "I will have an update tomorrow," "I will contact the director again," "I will call you tomorrow with an update."
Very unprofessional behavior by the management and the HR. Total waste of time and resources.
I hope higher management looks into this "Ghosting Trend" and improves on their side.
The following metrics were computed from 2 interview experiences for the Micron Technology Design Verification Engineer role in San Jose, California.
Micron Technology's interview process for their Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Micron Technology's Design Verification Engineer interview process in San Jose, California.