Got a call for a phone interview appointment two weeks after applying online. First was a phone interview with a panel of three; later, two weeks after that, an onsite interview invitation to Boise.

Phone interview questions were about yourself, your current job role, why this position, how you can relate to this position, the difference between a latch and FF, NMOS working, 3 NMOS in series (calculate output voltage across the 3rd NMOS), and a few more basic device physics questions.

Onsite interview was divided into 4 rounds.

First round with a panel of 3, about 3-D cross-point memory, its working (as it was for 3-D cross-point PE), logic questions, C code-based questions (recursion), about my present project (SerDes Rx blocks), how to validate a particular block in the SOC when you can't control the design parameters. Validation and verification concepts (I'm more into a design engineering background, so I couldn't answer validation/verification concepts), logic questions, programming (recursion) with address shift (LSB), nmos working.

Later, lunch with a senior engineer with regular questions about my experience and background.

Next, another 3-person panel interview, more into technical aspects: Id with respect to Vgs for NMOS, decoder circuit design (digital circuit design, boolean expression, realizing an AND gate-based circuit), a transmission gate (advantage over NMOS), current mirror and load resistors on both sides, R and 100R of it, how to validate it, and a few more basic questions which were more into verification/validation perspective.