Today, I want to share interview insights of an ASIC Verification Engineer. On May 5, 2024, I received a call for the interview of an ASIC verification engineer at Infinera. It was for an intern position.

Although I come from an Embedded Systems background, it was an arduous task for me to crack that interview. I wasn't selected because of my less attractive profile towards the VLSI domain, but that is not the end. I will significantly improve my profile until I achieve my goal.

The one thing that the interviewee asked was to verify a block of test code that was in Verilog. He just showed me a digital signal and then asked me to verify that waveform according to the design. For this case, I need to write a Verilog testbench.