ASIC Clock Interview Experience - New York, New York
Process
The interview was approximately one hour long.
From the interview, what I felt is that in ASIC design, scripting is more required rather than having full knowledge of hardware.
Nowadays, from my interview experience, the industry doesn't even use Verilog. Everything is done via scripting.
Questions
Construct an AND gate using a 2:1 multiplexer.
Construct a 2:1 multiplexer using AND, OR, and XOR gates.
Possible solution vectors to meet setup timing. Possible solution vectors to meet hold violation.
This was the main interview question: Design a subroutine (pseudo-code) that takes a variable-length array whose elements are in consecutive order but has one missing element. The minimum length of the array should be 2. The first and last elements cannot be missing.
What is the time complexity of the above subroutine?
How do you reduce the time complexity from O(n) to O(log₂n) for the above subroutine?
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Interview Statistics
The following metrics were computed from 1 interview experience for the Nvidia ASIC Clock role in New York, New York.
Success Rate
Nvidia's interview process for their ASIC Clock roles in New York, New York is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very good feelings for Nvidia's ASIC Clock interview process in New York, New York.
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