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ASIC Design Engineer Interview Experience - Santa Clara, California

March 1, 2024
Positive ExperienceNo Offer

Process

It started with a first call with the team manager, where he asked about basic multiplier and FSM questions.

Second round with a team member involved latch inference questions and a palindrome problem.

Questions

Design a two-bit single-cycle multiplier.

Write code to check if a string is a palindrome.

Design an FSM to count a series of 1's. The FSM should have a single-bit input per clock cycle. The series of 1's must start and end with a 0.

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Interview Statistics

The following metrics were computed from 14 interview experiences for the Nvidia ASIC Design Engineer role in Santa Clara, California.

Success Rate

29%
Pass Rate

Nvidia's interview process for their ASIC Design Engineer roles in Santa Clara, California is very selective, failing most engineers who go through it.

Experience Rating

Positive86%
Neutral14%
Negative0%

Candidates reported having very good feelings for Nvidia's ASIC Design Engineer interview process in Santa Clara, California.

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