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ASIC Design Engineer Interview Experience - Santa Clara, California

May 28, 2020
Positive ExperienceNo Offer

Process

Applied online.

Had two rounds of phone interviews, including usual screening and hardware questions.

Had an onsite that included design-based questions, a few coding problems, and some behavioral questions.

Questions

Phone Interviews:

  • CMOS basics
  • Usual gate/logic using one gate
  • Timing related questions
  • FIFO depth
  • Max in array
  • Palindrome

Onsite:

  • CDC: A lot on various techniques and improvements from one to another
  • Clock MUX logic
  • Clock dividers
  • FSM
  • Timing related questions based on designs above

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Interview Statistics

The following metrics were computed from 14 interview experiences for the Nvidia ASIC Design Engineer role in Santa Clara, California.

Success Rate

29%
Pass Rate

Nvidia's interview process for their ASIC Design Engineer roles in Santa Clara, California is very selective, failing most engineers who go through it.

Experience Rating

Positive86%
Neutral14%
Negative0%

Candidates reported having very good feelings for Nvidia's ASIC Design Engineer interview process in Santa Clara, California.

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