After writing the test at a university career fair, I received an email from HR for a phone interview.

Had two technical rounds, each lasting 45 minutes.

The first round was conducted by the hiring manager, who asked basic questions on Verilog coding, caches, pipelines, data forwarding, branch prediction, and FIFO design.

The second interview was tougher, with questions on instruction cache hit latency, multi-threading, branch misprediction, livelock, setup time, hold time, clock skew/jitter, Dennard scaling and its issues, and different transistor-level implementations of a multiplexer.

The whole process took three months, and I had to constantly contact HR for an update on my status.

How is processor performance affected when the instruction cache hit latency increases?

How do you overcome that?

What are the different ways of implementing a multiplexer at the transistor level? Compare them in terms of least delay.