Questions related to assertions, experience, and random block test planning.
The first round is a coding round, followed by 4 face-to-face rounds:
Assertion questions related to a protocol: develop all scenarios and write assertions.
Assertions, SystemVerilog, and UVM questions
The following metrics were computed from 10 interview experiences for the Nvidia ASIC Design Verification Engineer role.
Nvidia's interview process for their ASIC Design Verification Engineer roles is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Nvidia's ASIC Design Verification Engineer interview process.