I applied through an employee referral. The process took 2 months.

First Screening Round

• 2 basic RTL Questions, 1 Scripting
• Blocking vs non blocking, reg vs wire
• Python scripting question: file I/O, basic string parsing
• 2nd RTL question: Basic 2 stage adder, design Verilog module given circuit description
• Some resume questions

Second Screening Round

• Advanced scripting question on retiming registers
• RTL question on accumulating data per address
• Some theoretical FIFO questions (no code)
• Packed vs unpacked arrays in depth

Panel Round First Round

• Basic scripting question on data conversion and string parsing (CSV)
• Open-ended question on finding an error in a mux-based programmable delay circuit
• Resume questions

Second Round

• Designing a 10:1 mux using 3 4:1 muxes
• 80:20 to 8:2 module, FIFO depth

Third Round (Hiring Manager)

• Fibonacci Sequence in Python: Iterative and Recursive
• Fibonacci Sequence in Verilog: Serial approach, FSM Design
• Detailed discussion about team functions, responsibilities, day-to-day job

Fourth Round

• 4x4 multiplier in Verilog
• Optimize to pipeline multiplies
• Optimize to use a single MAC unit and serially feed in data
• Second largest sum in a Python list

Fifth Round

• Debugging a Perl script
• A lot of questions about intermediate expressions in Verilog and data-loss

First Screening Round:

• 2 basic RTL Questions, 1 Scripting
• Blocking vs non-blocking, reg vs wire
• Python scripting question: file I/O, basic string parsing
• 2nd RTL question: Basic 2-stage adder, design Verilog module given circuit description
• Some resume questions

Second Screening Round:

• Advanced scripting question on retiming registers
• RTL question on accumulating data per address
• Some theoretical FIFO questions (no code)
• Packed vs unpacked arrays in depth

Panel Round

First Round:

• Basic scripting question on data conversion and string parsing (CSV)
• Open-ended question on finding an error in a mux-based programmable delay circuit
• Resume questions

Second Round:

• Designing a 10:1 mux using 3 4:1 muxes
• 80:20 to 8:2 module, FIFO depth

Third Round (Hiring Manager):

• Fibonacci Sequence in Python: Iterative and Recursive
• Fibonacci Sequence in Verilog: Serial approach, FSM Design
• Detailed discussion about team functions, responsibilities, day-to-day job

Fourth Round:

• 4x4 multiplier in Verilog
• Optimize to pipeline multiplies
• Optimize to use a single MAC unit and serially feed in data
• Second largest sum in a Python list

Fifth Round:

• Debugging a Perl script
• A lot of questions about intermediate expressions in Verilog and data-loss