2 Screenings:
5 hours of onsite interviews with the physical design team.
Inverted temperature effect on STA. The question was based on temperature effects on delay below 65nm technology. How does STA work under those conditions at different corners?
An interesting question about how latency affects jitter.
Maximum skew allowed when lock-up latches are used.
OCV and questions based on it.
CRPR.
How does a cell get its minimum and maximum delay?
SPEF file contents, questions about StarRCxtractor working.
Internship experience-based questions.
The following metrics were computed from 1 interview experience for the Nvidia ASIC Physical Design Engineer (Hardware Engineer) role in Santa Clara, California.
Nvidia's interview process for their ASIC Physical Design Engineer (Hardware Engineer) roles in Santa Clara, California is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Nvidia's ASIC Physical Design Engineer (Hardware Engineer) interview process in Santa Clara, California.