One Zoom with Python OOP and then a Verilog FSM implementation. Next round was five 1-hour back-to-back in-person, whiteboard provided, Verilog mostly, also Python (LC med), and computer architecture (caches). They wanted someone with more UVM experience, I think.
flatten list to sum in python
The following metrics were computed from 18 interview experiences for the Nvidia ASIC Verification Engineer role.
Nvidia's interview process for their ASIC Verification Engineer roles is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Nvidia's ASIC Verification Engineer interview process.