Interviewed in Santa Clara.

5 people interviewed, about 4 hours.

The interview process consists of several stages:

1. HR Interview: Questions will cover reasons for applying to Nvidia, expected salary, immigration status, and graduation date, among other topics.

2. Verification Interview: Expect questions on verification methodologies (UVM, OVM), SystemVerilog concepts such as passing objects as function arguments, different types of fork-join, polymorphism, and the use and function of interfaces in testbenches.

3. Arbiter/Logic Design Interview: This stage focuses on arbiter design, setup/hold times, and basic logic design principles.

4. Programming Interview: You will be asked about programming concepts, including how to find loops in a linked list, basic C programming, and designing a divide-by-three divider.

5. Hiring Manager Interview: This conversation will focus on positions, teams, and their products. Expect questions on basic logic design, Verilog (synchronous, asynchronous, blocking, non-blocking), and transistor-level design of registers, including potential issues with such designs.

6. Informal Chat: This is a more relaxed discussion where the interviewer may talk about the team, their experiences, and their likes and dislikes about their job.

Most Difficult Challenge: Designing a divide-by-three divider with a 50% duty cycle proved challenging. Initially, I was unsure how to approach it. However, when the recruiter changed the requirement to a 66% duty cycle, I was able to complete the task.