The interview process consisted of two rounds.

The first round was primarily a screening, covering simple questions on digital design and computer architecture principles such as branch prediction, cache coherency, and pipelining.

The second round involved coding questions in Verilog and C++. It also included drawing the state machine for a hypothetical scenario, followed by coding the Verilog RTL for the correct solution.

Design a state machine that will print '1' when a binary string divisible by 5 is input. For example, '0101' and '1111' must all output 1.

Example verification cases for a two-port memory block with address, data in, data out, and a r/w enable.