The phone screen was average, but it had too many puzzles.
The five face-to-face interviews were on projects, SV, and UVM, but the interviewers always steered the discussion away from your area of expertise.
That's acceptable to some extent, but it becomes annoying when concrete questions are asked that require considering many factors beyond what the interviewer had in mind to select a correct implementation. The interviewers seem to want a clever answer, not necessarily the correct one. Additionally, some of their questions are vague, and they expect you to identify and answer all unasked, implicit sub-questions. They will then interrupt your explanation to pursue another tangential detail before you finish.
In programming and methodology interviews, they sought details found only in the nooks and crannies of reference manuals. They were dismissive of implementations other than their own, even when pros and cons were clearly outlined. On top of that, sophomoric puzzles and CS algorithm questions were introduced amidst serious discussions.
It appears they are looking for individuals who spend their time on puzzles and aim to appear smart. To navigate this interview style, one would need a comprehensive understanding of ASIC design (RTL and gate-level), verification, and data structures/algorithms. While most ASIC interviews are enjoyable regardless of rigor or outcome, this particular one was excessively tiresome. It seems this interviewing style has become a fad.
Test bench architecture, SystemVerilog minutiae, polymorphism in UVM, FIFO design (including the generation of control), details on clock domain crossing, clock gating, setup and hold times, flip-flops and resets, serial protocol and clock recovery, cache coherency, power saving methods, assertions, SoC verification techniques, data structures, sort and search algorithms, hashing algorithms and applications (as usual, an eternal fad).
Cover each "gotcha" point on all of the topics (all of which I answered correctly), but few with real depth or understanding. I got the feeling that they knew stuff as solutions to puzzles. When asked about their "solutions," they gave weak plausibility examples.
The following metrics were computed from 13 interview experiences for the Nvidia Verification Engineer role in India.
Nvidia's interview process for their Verification Engineer roles in India is very selective, failing most engineers who go through it.
Candidates reported having good feelings for Nvidia's Verification Engineer interview process in India.