Interview went very well. The folks were professional and punctual.

I am filling words here to meet the minimum criteria for this field. Ok, what else?

There were 5 rounds of onsite interviews plus 2 rounds of phone interviews. The questions were more focused on C++ and design, with very little SystemVerilog.

PHONE:

1. Pass by value vs. pass by reference. Write a function to swap two variables. Which method would you use?

2. Do the same to swap two objects. How does it change?

3. Detect the 11010 sequence with Moore and Mealy state machines.

4. Explain the use of const. What would happen if you declared the above two objects as const?

5. Explain NB assignment and blocking assignment. Discuss event regions.

6. Fibonacci: iterative solution and recursive solution.

7. Disadvantages of a recursive solution.

8. Output of this code fragment:

reg a, b, c, d, w; assign w = a;

initial begin a = 2; c = 5; b <= c; a = 5; end

What is the output of all registers?

1. Explain RISC pipelines. What are the problems?

2. Explain UVM drivers, etc.

ONSITE:

Round 1: Round Robin Arbiter Design.

Round 2:

1. Given a stack class implementation (LIFO) with three methods: push(), pop(), and isEmpty(). Write a class using objects of the given class to implement a FIFO.
2. Make the best performance. Implement the dist functionality in C++. Given a set of weights, mimic providing randomization skewed to the specification (Basically, write a function that would do something similar to dist in SystemVerilog).

Round 3:

Given a divide by 3 state machine. Implement a divide by 5 state machine. How many vectors are needed to verify it? The circuit takes serial bit inputs and asserts if the number is a multiple of 3 or 5.

Round 4:

Circuits project: Basic pipeline architecture. Design a pipeline for a histogram processor. In every cycle, we get an instruction (CLR, ADD, INCR). Handle dependencies using bypass.

Round 5:

Given a producer and a consumer. They are clocked with the same clock. The producer produces 80 writes for 100 clocks (no random). The consumer reads 8 times per 10 clocks. Find the FIFO depth. Write RTL and verify.