The interview process involved a lot of hands-on Verilog coding, including questions about RTL design for FIFO.
They also asked some technical concepts like:
Constrained-random assertions for different requirements including randc.
The following metrics were computed from 6 interview experiences for the Nvidia Verification Engineer role in Santa Clara, California.
Nvidia's interview process for their Verification Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Nvidia's Verification Engineer interview process in Santa Clara, California.