Awesome, best in ESPP and RSUs.
Heavy work during chip tapeout times.
It was an okay type of interview. It was a normal interview. There were three people in the interview. Two of them were asking questions. They asked me five questions: * One question was from the written test. * One question was from Verilog.
It was an on-campus drive with two rounds: an online assessment (OA) followed by a technical interview. The technical round was difficult, consisting mostly of questions on digital electronics, digital logic design, and static timing analysis. If yo
It was an on-campus interview. There was an OA related to ECE core subjects. After that, you have a virtual interview based on the depth of digital electronics. The interview was all about digital electronics, clock signals and timers, and waveforms
It was an okay type of interview. It was a normal interview. There were three people in the interview. Two of them were asking questions. They asked me five questions: * One question was from the written test. * One question was from Verilog.
It was an on-campus drive with two rounds: an online assessment (OA) followed by a technical interview. The technical round was difficult, consisting mostly of questions on digital electronics, digital logic design, and static timing analysis. If yo
It was an on-campus interview. There was an OA related to ECE core subjects. After that, you have a virtual interview based on the depth of digital electronics. The interview was all about digital electronics, clock signals and timers, and waveforms