The ESPP plan has a 2-year lock period and gave good returns over the past few years. The CEO is a very interesting and empathetic person.
Lack of management support, coupled with very high expectations, ruins WLB. Lower ICs are also expected to perform at the level of managers. Sometimes, they are very cruel in giving feedback.
Please don't induce stress in employees.
Managers are taking every employee mistake as an opportunity to give negative feedback. There's no talk about positive contributions in focal conversations. It demotivates and discourages us from improving and doing our best work.
Managers lack empathy, and the CEO is very employee-friendly. So, managers are resorting to brutal ways to find faults and push people away from the company.
The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Initial communications, process, and follow-ups were good. The interview process was organized very well. Technical rounds covered basics to advanced topics, including verification, STA, design, and etc. They looked at whether I had worked on verif
The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.
The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Initial communications, process, and follow-ups were good. The interview process was organized very well. Technical rounds covered basics to advanced topics, including verification, STA, design, and etc. They looked at whether I had worked on verif
The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.