There are lots of things to learn.
There are lots of projects to do.
There are opportunities in many fields.
One can do design work, verification, or FPGA.
All are there.
Too much politics. Too much emphasis on email and bug reports. The "Rally" tool sucks the life out of you. Middle management is clueless. Not good pay.
Fire dumb managers and employees. Reward good ones.
The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Initial communications, process, and follow-ups were good. The interview process was organized very well. Technical rounds covered basics to advanced topics, including verification, STA, design, and etc. They looked at whether I had worked on verif
The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.
The interview process consisted of two tech screens, followed by a panel. Interview questions were standard design problems, targeting both Verilog coding ability and problem-solving skills. Interviewers looked more at thought process than specific s
Initial communications, process, and follow-ups were good. The interview process was organized very well. Technical rounds covered basics to advanced topics, including verification, STA, design, and etc. They looked at whether I had worked on verif
The interview was managed very professionally. The questions asked were purely technical and related to the basic fundamentals of electronic design/chip design.