ASIC Design Engineer Interview Experience - San Jose, California
December 6, 2024
Positive ExperienceNo Offer
Process
It's an NCG role, so not that hard. Coding involves Frequency division, reorder buffer and Round robin arbiter. Asked me to do some gate-level drawing. Questions about STA and synthesis.
Questions
How to do CDC, and why use gray codes?
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Interview Statistics
The following metrics were computed from 1 interview experience for the NXP Semiconductors ASIC Design Engineer role in San Jose, California.
Success Rate
0%
Pass Rate
NXP Semiconductors's interview process for their ASIC Design Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Experience Rating
Positive100%
Neutral0%
Negative0%
Candidates reported having very good feelings for NXP Semiconductors's ASIC Design Engineer interview process in San Jose, California.
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