I received a call after applying through my university. I was phone screened, and various standard textbook questions were asked for one hour. The interviewer tested the breadth of my knowledge across circuits, RTL & implementation, and architecture.

On the basis of my performance in the interview, I received multiple calls from various teams spanning architecture, circuits, and verification. I agreed to interview with a few of them based on their job descriptions and was called for an onsite interview, where the depth of knowledge is checked by all the teams.

The interviews were mostly a grilling, with each team taking up to four rounds of one-on-one interviews. The results were given in just 2-3 days, and multiple teams could make an offer. Salary and perks negotiations begin only once you give a green signal to a particular team.

Basic RTL questions on FSMs.

Full VLSI flow from synthesis to GDS.

Clock gating.

SRAM internal circuits.

STA (Static Timing Analysis) timing questions.

Inverter and buffer characteristics.

Low power methodologies.

NAND gate implementation of gates, and timing and layout.