Hardware Engineer - FPGA Verification Interview Experience - Sunnyvale, California
Process
I found the recruiter on LinkedIn and got an interview the next day. People in this company should learn some basic manners.
The recruiter didn't call at the agreed-upon time for our phone conversation... twice! They kept me waiting in the lobby for half an hour and then finally told me I was in the wrong building. The team didn't even try to find me during that half hour.
In the interview schedule, I was supposed to talk to the recruiter at the end so I could ask some questions. When I got there, they told me the recruiter wasn't even in the office that day.
Questions
Questions about SystemVerilog, OOP concepts.
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Interview Statistics
The following metrics were computed from 1 interview experience for the Palo Alto Networks Hardware Engineer - FPGA Verification role in Sunnyvale, California.
Success Rate
Palo Alto Networks's interview process for their Hardware Engineer - FPGA Verification roles in Sunnyvale, California is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having very negative feelings for Palo Alto Networks's Hardware Engineer - FPGA Verification interview process in Sunnyvale, California.
Palo Alto Networks Work Experiences
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Palo Alto Networks Interview Questions
