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ASIC Design Interview Experience - San Diego, California

May 1, 2010
Neutral ExperienceNo Offer

Process

I received a call from a manager. He asked me several questions, such as:

  1. Transistor size for a NAND gate.
  2. Maximum and minimum timing violations.

Questions

Transistor sizing for a NAND gate.

Min and max timing violation.

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Qualcomm ASIC Design role in San Diego, California.

Success Rate

0%
Pass Rate

Qualcomm's interview process for their ASIC Design roles in San Diego, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral50%
Negative50%

Candidates reported having very negative feelings for Qualcomm's ASIC Design interview process in San Diego, California.

Qualcomm Work Experiences