I received a call from a manager. He asked me several questions, such as:
Transistor sizing for a NAND gate.
Min and max timing violation.
The following metrics were computed from 2 interview experiences for the Qualcomm ASIC Design role in San Diego, California.
Qualcomm's interview process for their ASIC Design roles in San Diego, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Qualcomm's ASIC Design interview process in San Diego, California.