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Design Verification Engineer Interview Experience - San Jose, California

October 1, 2020
Negative ExperienceNo Offer

Process

The screening interviewer for this media processor group was a shady, Indian, H1B employee from Texas. He was not the hiring manager but kept asking illegally about my compensation expectations and whether I would be willing to relocate to a different location than the primary job location in Santa Clara, CA.

I answered all the technical questions properly but never heard from Qualcomm again. It baffled me being ghosted without any updates, but then I realized this individual's intent was to block better candidates from joining his group to protect his position and job security at Qualcomm.

This behavior of working against his employer's interests was unfortunate and unethical. It happened because one's case can be easily lost in the pool of candidates without management or HR being able to check or audit it.

Questions

SystemVerilog (polymorphism, constraint, assertion), UVM, test plan

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Interview Statistics

The following metrics were computed from 1 interview experience for the Qualcomm Design Verification Engineer role in San Jose, California.

Success Rate

0%
Pass Rate

Qualcomm's interview process for their Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral0%
Negative100%

Candidates reported having very negative feelings for Qualcomm's Design Verification Engineer interview process in San Jose, California.

Qualcomm Work Experiences