I had two rounds of interviews: the first was telephonic, and the second was on-site with five team members.

I was initially contacted by the hiring manager for a phone interview and received the job description.

After scheduling, the call lasted for about 45-50 minutes. The interviewer asked various design questions, including timing, setup time, hold time, synthesis flow, and input/output delay.

After all the questions, I asked the interviewer about the position in detail. They confirmed the role would focus on front-end ASIC design, synthesis, and timing analysis, as indicated in the job description.

After a week, HR contacted me for a further interview (on-site) and provided me with the job description details again (Design).

Upon arriving at the office, the first interviewer asked me some verification questions and OOPS concepts. I was surprised.

Later, I was told I was being interviewed for a design verification position. All subsequent rounds included verification questions and some design questions. They asked about OOPS concepts, SystemVerilog, assertions, arrays, test plans, and AMBA Buses.

Synchronous and Asynchronous FIFO Design and Verification.

Write assertions to verify the conditions.