Taro Logo

Senior Engineer Interview Experience - Bengaluru, Karnataka

June 1, 2024
Positive ExperienceGot Offer

Process

They conducted one screening call, followed by four face-to-face rounds in a single day. Continuous rounds can be draining, leading to a loss of energy. However, it was a very good experience.

After two weeks, they informed me of my selection. It then took an additional two weeks to release the offer.

Questions

  1. What CDC techniques do you know? Explain fast to slow, slow to fast, edge, toggle, and pulse.
  2. What CDC issues have you faced?
  3. Explain synchronous and asynchronous reset. Explain Reset Domain Crossing.
  4. If an asynchronous reset from an asynchronous domain is used as a synchronous reset in another clock domain, how will you handle it?
  5. Explain latch-based clock gating.
  6. If two clocks are multiplexed using a control signal, how will you handle it?
  7. Calculate FIFO depth. Wr = 100MHz, Rd = 50MHz, Burst = 120
  8. What timing constraints have you used while doing synthesis?
  9. Sequence detector - 1001 with overlapping using Moore - Verilog code.
  10. Sequence detector - 1011 with overlapping using Mealy - Verilog code.
  11. Explain RISC-V Architecture. What is your role? Discuss bypass and stall operations, and WBMUX features.
  12. How will it be realized with hardware? Two states - a and b. Initial state is a. If ctrl is 0, it remains in a. Else, go to b (op=1). If it's in state b, if ctrl is 0, it remains in b. Else, go to a (op=1).
  13. Write pseudocode for the Fibonacci sequence.
  14. A CPU receives interrupt pulses from different IPs. How will it sample them inside the CPU? We don't have any idea at what rate I am receiving these pulses, but the CPU needs to detect them.
  15. Write the equations for setup and hold time. Why does hold time not depend on the clock?
  16. Given one STA problem, calculate the maximum clock frequency and combo delay. Tse, Th, Tcq, Tskew are given.
  17. Issues related to convergence. What is convergence?
  18. Related to Lint issues, how to fix combinational loops?
  19. Which FSM style is mostly used in industry? How will you declare FSM states? What is the difference between one-hot and binary encoding? Which is better to use and why?

Was this helpful?

Interview Statistics

The following metrics were computed from 19 interview experiences for the Qualcomm Senior Engineer role in Bengaluru, Karnataka.

Success Rate

79%
Pass Rate

Qualcomm's interview process for their Senior Engineer roles in Bengaluru, Karnataka is incredibly easy as the vast majority of engineers get an offer after going through it.

Experience Rating

Positive84%
Neutral11%
Negative5%

Candidates reported having very good feelings for Qualcomm's Senior Engineer interview process in Bengaluru, Karnataka.

Qualcomm Work Experiences