I applied via LinkedIn. A manager from QC reached out to me.

The first round did not go well, but my skills were in line with the responsibilities, so it was forwarded to the next round.

The second round focused mostly on my resume and the skills listed. Some questions were asked about multiprocessor systems and UVM test-bench design around that.

The third round involved some test-bench design and explanations for a similar multiprocessor system.

The fourth and fifth rounds were with "US guys" (as phrased in the original text) on GPU knowledge and extensive coding (from scratch) using UVM.

The last round was HR staffing, in which some behavioral and situational questions were asked.

Overall, the interview experience was amazing.

Virtual Methods, Virtual Classes, and their differences in SystemVerilog.

Questions on UVM concepts:

• Sequencer-driver communication
• Monitors
• Scoreboards
• Coverage

Object overriding and overloading. Callbacks, mailboxes, and semaphores.

How to design a UVM testbench for a given design. What components are needed, etc. Corner cases to test out and efficient ways to build environments.

Coding the basic skeleton code for a given design. All UVM components should be coded and explained. This includes monitors, scoreboard logic, DUT, agents, sequence items, sequences, drivers, and tests.

Questions around the GPU pipeline and how it works. Command streamer, etc.

Questions on basic debugging skills using Synopsys VCS. OOP concepts. Ethernet, AXI, APB protocols and their usage. Protocol bridges.